Recently, MOS dynamic RAMs (hereinafter referred to as DRAMs) having a large storage capacity on the order of a mega-bit have been realized. In keeping with such a trend, DRAMs have been designed to achieve higher density by reducing the size of the memory cells contained therein.
The present invention relates to a MOS capacitor and a method of manufacturing it, and in particular, to a MOS capacitor suitable for increasing the density of a DRAM and a method of manufacturing such a MOS capacitor.
With progress in the study of means for increasing the degree of integration of the DRAM, a DRAM having a capacity as large as several mega-bits has been reported. However, since the size of a chip generally increases as the storage capacity is increased, in order to achieve practical use, it is necessary to increase the density by further reducing the size of the memory cell.
The area of the memory cell per 1 bit is in a range from 50 to 70 .mu.m.sup.2 for a DRAM of 256 kb, and the area must be reduced to a range from 20 to 30 .mu.m.sup.2 or less for 1 Mb. However, taking a soft error and noise margin into consideration, it is necessary that the capacity of a capacitor constituting the memory cell be made substantially comparable to the DRAM of 256 kb.
In order to maintain the capacity of the capacitor of the memory cell comparable to that of the DRAM of 256 kb while reducing the memory cell area, there is a method in which the effective film thickness of an insulating film (hereinafter referred to as a capacitor insulating film) which is a constituent element of the capacitor is reduced, or another method in which the effective area of the capacitor insulating film is increased.
However, in the former method, since it is difficult to make a silicon dioxide film thinner than about 10-15 .mu.m in view of pinholes and the like, there exists a limitation.
On the other hand, a trench-shaped capacitor is known in which, in order to eliminate the drawbacks mentioned above, a trench of several .mu.m in depth is formed in the semiconductor substrate, and by forming a capacitor on the inner wall of the trench, the effective area of the capacitor is increased (e.g., Kiyoo Itoh et al, "256 k/l Mb DRAMS-II", 1984, ISSCC, pages 282-288).
The trench-shaped capacitor of this structure is a kind of MOS capacitor structure in which an element isolation region is formed in the silicon substrate by a selective oxidation method, trenches are formed adjacent to the element isolation region and sandwiching this region, insulating films are respectively formed on inner walls of these trenches, and the trenches are filled up by forming polycrystalline silicon films on the insulating films so that the insulating films constitute dielectric layers and the silicon substrate and the polycrystalline silicon films are used as electrodes.
The trench-shaped capacitor mentioned above is designed to reduce the area of the memory cell by forming the trenches in the silicon substrate and forming the capacitor on the inner walls. However, when the trench-shaped capacitors are formed adjacent to both sides of the element isolation region formed by the selective oxidation method, punch-through will be caused between the adjacent capacitors, and reducing the isolation width will become difficult. Moreover, since the selective oxidation method is employed in the element isolation, there arises a problem in that the generation of a "bird's beak" can not be avoided and higher integration can not be achieved.
Furthermore, a crystal defect or the like will occur in the silicon substrate during the trench forming process and the heat treatment process will cause a leakage in the substrate and a defect in the capacitor insulating film. These problems pose a large obstacle in manufacturing a large capacity memory.